1. Technical Field
The present invention relates generally to an apparatus and method for detecting the fault of a processor and, more particularly, to an apparatus and method that detect and correct the fault of a processor when the fault has occurred.
2. Description of the Related Art
Processors read and analyze instructions stored in external storage devices, and perform specific operations using operands designated by the instructions. Furthermore, the processors store the execution results of the specific operations in the external storage devices, and perform specific functions using stored programs.
A processor includes a fetch unit, a decoding unit, an execution unit, and a register file.
The fetch unit functions to read an instruction to be executed from memory (an external storage device) and transfer the instruction to the decoding unit.
The decoding unit analyzes the received instruction, operates a required arithmetic and logic unit (ALU) of the execution unit, and makes the input of the ALU be read from the register file.
The execution unit transfers an operand read from the register file to the corresponding ALU, and makes the operation result of the ALU be stored in the memory or register file.
The register file reads data from or writes data into memory, reads an operand stored as information received from the decoding unit, and transfers the operand to the execution unit.
A fault may occur in the fetch unit, the decoding unit, the execution unit and the register file, and may influence the processing results of the processor.
As related technology, Japanese Patent Application Publication No. 2009-015590A discloses an apparatus for detecting the fault of multiple cores that is capable of determining the operating status of each processor core.
While Japanese Patent Application Publication No. 2009-015590A discloses the configuration of a device in which multiple processor cores have been employed, it does not disclose technology for the detection of a fault in each unit of the processor cores.